The semiconductor industry is continuously reducing the dimensions of devices. There is particular interest in minimizing the size of conductive layers in back-end-of-the-line (BEOL) processing. BEOL processing includes a portion of integrated circuit fabrication where the active components (transistors, resistors, etc.) are interconnected with wiring on a wafer. The BEOL process generally begins when the first layer of metal is deposited on the wafer. It includes contacts, insulators, metal levels, and bonding sites for chip-to-package connections.
With achievement of finer semiconductor processes, the integration and concentration of circuits in a microchip has significantly increased. While such advances provide greater capabilities, the more compact integration also narrows the spacing between circuit wires, or traces. This narrowing can increase parasitic capacitance between traces. Parasitic capacitance occurs when two adjacent traces on a microchip draw electrical energy from one another. This phenomenon generates undesirable heat and slows the speed at which data can move throughout the microchip. The increase in parasitic capacitance between traces can result in crosstalk, where an electric signal leaks between traces. Power consumption may be increased, as may resistor-capacitor time delays between interconnecting traces, or interconnects. Resistor-capacitor time delays can significantly reduce the operating speed of microchips. Such delays can also cause signals to arrive outside of designed timing margins, disrupting microchip performance.
Airgaps were developed in microelectronic fabrication by International Business Machines Corporation (IBM) to address these problems. Airgaps typically comprise vacuumed voids in the silicon dioxide substrate adjacent at least one side of a trace. The airgaps reduce the amount of capacitance between traces in the multilayer design of the microchip. Capacitance can be minimized by insulating copper wires or other conductive traces of a microchip with the vacuumed airgaps. The airgaps have a lower dielectric constant than silicon dioxide. The extremely low dielectric constant of air, i.e., “1,” makes it an ideal dielectric medium for lowering the capacitance between the narrow trace configurations. The reduced capacitance of the airgap functions to increase timing margins, as well as frequency targets. The minimization of the capacitance enables microchips to work faster and draw less power.
IBM has developed a way to manufacture airgaps on a massive scale. Such processes may use the self-assembly properties of certain polymers combined with complimentary metal-oxide-semiconductor (CMOS) manufacturing techniques. During semiconductor production, the entire wafer may be prepared with a polymer material. When the polymer material is removed, trillions of selectively positioned airgaps may result. Such exemplary airgaps may be around 20 nanometers in diameter and evenly spaced.
Despite such advances in airgap fabrication processes, the hardware, masks for each layer, polymer material, software, skilled labor and processing costs represent additional costs to standard microchip design and manufacture expenses. Although airgaps are the best dielectric structures for lowering capacitance, they can thus be relatively expensive to fabricate. The additional costs associated with incorporating airgaps into the fabrication process may discourage their use. Such a reluctance may translate into the potential performance benefits of airgaps being unrealized.
A need consequently exists for an improved manner of designing and fabricating airgaps in a microchip.